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1 features ? programmable resolution, active cmos imager for video and still operation pc plug-and-play capable in usb mode full 16-bit digital interface for simple, fast transfer in parallel-port mode low, fixed-pattern noise triple 10-bit adcs and column-based cds for high-quality display high fill factor and sensitivity without microlens distortions available in color or black-and-white versions integrated avr ? 8-bit advanced risc microcontroller for system control easy register-based programming modes region-of-interest image scan control for digital zoom and metering on-board color offset and gain control on-board gamma lookup table available full power control and low-power viewfinder mode master or slave mode operation description the atmel AT76C402 is a complete image capture and processing system that has been designed to give quality images using a standard interface with simple opera- tion. this highly-integrated solution provides a product with reduced system cost and rapid time-to-market. the AT76C402 has two interface modes: usb and parallel port. both use the device as a slave. this datasheet covers usb mode only. see the ?AT76C402 ? parallel port mode? datasheet (literature number 1372) for parallel port mode pinouts and operation. the image capture core is a pixel array of 300 x 300 rectangular active pixels with a high physical fill factor of 43% (without micro lenses). a vertical stripe rgb pastel color filter is used with individual column-correlated double sampling (cds) correction circuitry to produce an exceptionally low level of fixed-pattern image noise (fpn). indi- vidual color gain and offset controls followed by a triple 10-bit analog-to-digital converter further assure an even color response in the digitized images. region-of-interest mode additionally allows the user to define on a frame-by-frame basis the area of the imager to be read, enabling easy digital zoom or complex multi- spot metering routines utilizing an external host. the data path from the imager is through the gain/offset and adc block and the lookup table into a 1k x 8 fifo. the value written into the fifo is truncated to eight bits. the data is then read by the avr and passed either via the usb ping-pong fifo to a usb pad or via a custom 16-bit parallel port. timing and control is handled by an on-chip avr 8-bit microcontroller and timing gen- erator. the avr executes firmware uploaded into an on-chip 4k x 16 sram via a serial peripheral interface (spi) during device power-up. the spi is designed to work with off-chip eeprom or flash memory. the avr uses an on-chip 2k x 8 sram scratch pad for data operations. in master mode the avr controller still boots from an external eeprom/flash, but writes the image data back through the spi into the eeprom/flash. the avr com- municates control via the gpio port which is connected externally. this provides a lower component cost solution for applications which are not transfer time dependent. master mode is not described further in this datasheet. usb and parallel port mode integrated cmos imager AT76C402 ? usb mode preliminary rev. 1360a?06/00 www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 2 pin configuration figure 1. AT76C402 die view ? usb mode top view 69 68 67 66 61 62 63 64 65 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 avdd5 iref vdd5 vdddc vddac agnd gnddc vddac avdd gndac gndac avdd avdd avdd_reg agnd vdd_reg agnd gndac vddac gnddc gndac vdddc vddac ee_so ee_cs gnddc vdddc ee_sclk ee_si lft d0p d0m xin xout ee_prgm vddac gndac gnddc vdddc ee_mode 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 87 88 89 90 91 92 93 94 95 96 97 98 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 99 i_iar i_iag i_iab o_iar o_iag o_iab www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 3 note: for parallel port pinout, refer to parallel port mode datasheet (lit. no. 1372). table 1. usb mode pin and pad description pin number pad names type description 1, 30, 50, 83 vdddc digital power 3.3v digital dc power ? core 2, 31, 52, 82 gnddc digital ground 0.0v digital dc ground ? core 7, 51, 59, 71, 91 gndac digital ground 0.0v digital ac ground ? pad ring 8, 49, 58, 70, 92 vddac digital power 3.3v digital ac power ? pad ring 18 ee_prgm digital input mode select for flash or eeprom programming 19 xout analog out 16 mhz crystal 20 xin analog input 16 mhz crystal 21 d0m data - usb differential pad 22 d0p data + usb differential pad 23 lft analog input pll low-pass filter terminal 33 ee_si tri-state digital output serial peripheral interface signal output 35 ee_sclk tri-state digital output serial peripheral interface clock output 37 ee_cs tri-state digital output serial peripheral interface chip select output 39 ee_so tri-state digital input serial peripheral interface signal input 79 ee_mode digital input select for external eeprom or flash 97 vdd_reg digital regulator 3.3v output for de-coupling 98 vdd5 digital regulator 5v input 99 avdd_reg analog regulator 3.3v output for de-coupling 100 avdd5 analog ground analog regulator 5v input 101, 102, 110 agnd analog ground ground rail for analog and pixel array 109, 123, 124 avdd analog power supply rail for analog and pixel array 111 i_iar current input red channel from gamma 112 i_iag current input green channel from gamma 113 i_iab current input blue channel from gamma 114 o_iar current output red channel to gamma 115 o_iag current output green channel to gamma 116 o_iab current output blue channel to gamma 117 iref analog in current reference for on-chip bias generators www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 4 block diagram figure 2. block diagram of AT76C402 table 2. physical and electrical parameters parameter measurement units resolution 300 x 300 pixels pixel size 12 (h) x 6 (w) m image area 3.6 x 1.8 mm fill factor 43 % max col fpn 0.2 % dynamic range 60 db power supply 3.3v 10% (parallel port mode) v power consumption < 100 mw readout rate 3 mpixels/second sensitivity(saturation) 20 ua/lux-sec conversion gain 1.05 na/e- dark current 0.3 @ room temperature na/cm 2 analog gain and offset look-up table line fifo usb core clock logic avr core program memory data memory usb pad image sensor array column decoder timing generator row decoder parallel port mux i/o bus address bus data bus control bus spi image sensor logic adc program download red blue green cds block optional gamma function analog in analog out www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 5 figure 3. board system architecture ? usb mode (AT76C402 with external components) 1 pixel (test) 300 pixels 9 pixels (dark) (0, 0) 21 pixels (dark) active 300 pixels + 2 pixels (r,g) pixels 1 pixel (test) (324, 310) (324, 0) 6.0um 12um red green blue image sensor array image acquisition die AT76C402 avdd agnd dvdd dgnd vddac gndac 3 3 5v supply crystal eeprom or flash usb data + usb data - host pc image camera system spi port data + data - ee_prgm usb port xout xin lft ee_cs ee_si ee_sclk ee_so xout xin ee_cs ee_si ee_sclk ee_so vdddc gnddc avdd agnd vddac gndac ee_prgm vdd gnd optional external gamma function o_qar o_oab o_oag i_iar i_iab i_iag 3 3 iref iref o_qar o_oab o_oag i_iar i_iab i_iag www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 6 architectural overview active pixel array the pixel array used is a three-transistor voltage mode photodiode design. to initialize the pixel, the reset transis- tor t rst (which is common with others across each row) is turned on, and the photodiode active area charges up to the v rstbias line. figure 4. pixel transistor schematic when t rst is turned off to start the integration, the photo- diode begins to discharge and theresulting voltage level is buffered by t buf through to the row select transistor t sel . after integration is complete, transistor t sel (also common with other t sel across the row) is turned on presenting the pixel voltage to the column readout bus. note that the photodiode will continue to integrate if still illu- minated or until it is reset again by activating t rst in preparation for another exposure period. see figure 4, figure 5, figure 6 and figure 7. figure 5. pixel select and reset timing figure 6. pixel cross-section figure 7. pixel charge potential plot v rstbias t rst t sel i load cds circuitry column decoder v out 80ke-/v cpd = 13if spd = 12.3muv/e t buf integration reset readout sel rst pd vout pd rst v rstbias active sel column i load +ve v 1v 2v .5v 2v .85v .1v 0v www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 7 correlated double sampling a cds block is placed at the bottom of every pixel column signal line. using the image timing generator, the photo- diode voltages from all of the pixels in a row are applied in parallel to their cds blocks, buffered, clamped and con- verted to a current. this is then stored in the first of two current memories in each block. column-correlated double sampling is then performed by turning on t rst , resetting the pixel and storing the reset voltage after buffering and conversion in a second current memory. finally, the difference in the two values, reset and signal- reset, is passed out of the cds block (still as a current value) onto one of the three color busses (red, green and blue for color; left, middle and right for black-and-white). these values are passed onto the gain/offset and adc block which can be programmed to provide gain and offset adjustment to the value. gain and offset individual gain and offset of the output of the cds busses are performed using six current mode amplifiers under the control of dacs driven by the contents of six registers in the avr i/o space. a seventh register (gain_mstr), through a single dac, is used to control three additional amplifiers ganged together to perform global gain. the red, green and blue channel output is defined by the equation: where g gain is the global gain f gain is the fine gain per channel offset is the offset correction per channel analog access port after gain and offset amplification the three color busses are made available (via register control) through ports o_oar, o_oag and o_oab as current signals at a con- stant voltage for external processing as required, for example a gamma function. these signals are reinserted into ports i_iar, i_iag and i_iab. see full pinout descrip- tion for location if required. it is not necessary (or desirable) to link the ports externally if this feature is not used as the signal can be bridged inter- nally under the control of the ana_ctl register in the avr i/o space. 10-bit analog-to-digital converter following the internal or external loopback, the three-color bus current signals are passed to three 10-bit pipelined analog-to-digital converters which require eight master clock periods for each conversion. a digital multiplexer, controlled from the image timing gen- erator, brings the digital image data out via a single 10-bit width data bus. bias generator there are on-chip voltage and current bias generators which provide all the necessary bias for the imager and analog blocks (gain/offset and adc block). an external resistor connected to iref provides a stable reference cur- rent value (e.g. 10k ohm across 1.25v provided gives 125 a for iref). the block can be powered down to conserve power. for more details, refer to the section ? power con- trol ? on page 13. lookup table the 10-bit data is compressed to 8-bits via either user- selectable linear truncation or the choice of two non-linear transfer functions stored in an on-chip lookup table (lut). the tables used in the lookup table are hard-wired and reg- ister-selectable. the linear truncation option is done on the eight most significant bits. the two non-linear options are gamma functions: lookup table a is an intermediate lookup table defined as: where n is a 10-bit input value and y is an 8-bit output value lookup table b is a logarithmic lookup table defined as: where n is a 10-bit input value and y is an 8-bit output value the lookup table can be bypassed if desired and the full 10-bit data can be brought out through the parallel port in parallel port mode. refer to the ? AT76C402 parallel port mode ? datasheet, literature number 1372. i out 2 g gain f gain i in offset ? = y 72.85 log 2 () 255 + ? = n 1 0.0884 ? 1023 --------------------------- 0.0884 + = y 25.5 log 2 n 1 + () ? = www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 8 row/column timing the imager scanning circuits, the row and column decod- ers, are under the control of the timing generator. in turn, the avr controls the generator function using the values stored in the avr i/o space register. these determine the region of interest to be viewed, the start and end locations and the exposure mode and exposure time. the values in these registers are uploaded into the device during power up. the imager scans from left to right and bottom to top; both still and video modes are supported. avr microcontroller this is a low-power 8-bit risc microprocessor based on a harvard architecture. it supports internal and external inter- rupts, sleep control and a rich 8-bit instruction set with 32 general-purpose working registers. all the registers are directly connected to the alu, allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the architecture supports high-level languages as well as extremely dense assembler programs usb controller the usb controller consists of a serial-interface engine (sie), a serial bus controller and a system interface. the sie performs the clock/data separation, nrzi encoding and decoding, bit insertion and deletion, crc generation and checking and the serial-parallel data conversion. the serial bus controller consists of a protocol engine and a usb device with a control end point and data end points. the serial bus controller manages the device address, monitors the status of the transactions, manages the fifo and communication to the microcontroller through a set of status and control registers. the system interface connects the serial bus controller to the microcontroller. the controller is a full-speed, 12 mbs transfer core designed to work with the avr microcontroller. it allows the usb host to configure the device and receive serial com- munication to and from the device. the controller supports three endpoints. the first, eb0, is the command 8-byte endpoint. the second, eb1, is the bulk transfer endpoint with a 64-byte ping-pong data fifo. this configuration allows for back-to-back data transfer and retransfer of packet data if required. the third, eb2, is the user-defined interrupt 2-byte endpoint. the usb registers are mapped explicitly to addresses in the sram memory space. communication with the controller is based on the universal serial bus specification version 1.0. line fifo the data from the imager via the adc can be wrtten into the fifo based on the avr i/o space register assigned to this function. the fifo enables the user to fill it with more than two lines of information, the controller can then start to read this data out and, while it does this, the fifo is filled with the next line of data. this feature increases data throughput. serial peripheral interface code from either an external eeprom or flash is down- loaded into the device on power-up using a 4-wire serial peripheral interface (spi). the selection between down- loading from either memory is determined by the status of the ee_mode pin, 0 for eeprom, 1 for flash. to program the device, ee_prgm must be toggled to 0 to load the code and switched back to 1 after programming for normal operation. functional description there is an additional option of writing image values or parameters to external flash. see ? external memory inter- face ? on page 18 for timing diagrams. scan control the AT76C402 integrates all the functions required to cap- ture, digitize and process an image. to allow maximum flexibility, the individual functions are register-programma- ble and are accessible via the avr i/o space. the user can therefore control precisely the various functional blocks to accomplish a customized operation. the image is read from bottom to top, left to right. a row decoder and counter controls the row read-out, and a col- umn decoder and counter control the column read-out. the row decodes a maximum of 310 and the column decoder a maximum of 108 (108 x 3 triplets = 324). the desired region of interest is defined using registers residing in the avr i/o space. these include the registers rst_start_row, sel_start_row, end_row, start_col and end_col. see ? avr i/o space regis- ter map ? on page 14 for names and addresses. internal image scan modes single still frame mode still frame operation is achieved using an electronic half shutter and is usually augmented by an external mechani- cal shutter for high-speed exposures. setting bit 2 = 0 of the image_capture_mode register in the avr i/o space selects still frame mode. the expo- www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 9 sure time is determined under external control and can be as short or as long as the user requires. after the exposure period (and possibly after the external shutter has been closed), the image is read out on a line- by-line basis starting with the lower left hand corner of the area defined in the sel_start_row and start_col registers until it reaches the values in end_row and end_col. the data is read out row-by-row at the rate as determined by the line fifo. the rst_start_row reg- isters are not used in this mode. the initialization and readout sequence is controlled under firmware. although a mechanical shutter may be used to prevent direct exposure after reading of the image has begun, the pixels will continue to integrate dark current. the readout period, once the shutter is closed, should therefore be kept as short as possible in relation to the exposure time to avoid a brightness gradient down the picture. if this is not possible due to system or transmission channel constraints then a simple algorithm can be implemented to correct for it. figure 8. timing diagram showing internal cds operation for still frame mode row reset(309:0) pixel signal sample column(107:0) column clamp row select(309:0) column power reset sample pixel reset sample pixel signal level pixel reset level 0 ? s0 ? s 2 r 2 r-1 2 r 2 c+m 2 c+1 2 c+2 2 c www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 10 moving blade mode for continuous image acquisition, exposure is controlled using a moving blade electronic shutter the width of which is written to the rst_start_row registers defined in the avr i/o space before a frame is exposed. figure 9. moving blade shutter indeterminate exposure exposure zone exposure region based on: rst_start_row to sel_start_row register value stop row moving blade shutter reset row n read start row n reset reset row wraps to start row before read row reaches stop row read row www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 11 figure 10. timing diagram showing internal cds operation for moving blade mode again, a region of interest can be defined using the start and end values for the row and column as defined in the avr i/o space. the reset register for the row in this case needs to be defined and the value between this and the select row register is the exposure line. the exposure can be calculated as: for the first frame valid data is not available until the pro- grammed exposure period for the first line has been reached. during this period, the last n (where n is the num- ber of lines of the exposure) lines of the imager are read out followed by the first frame sync. as these lines will have been reset at an indeterminate time, the data obtained will be random. to establish the true start of the image, the user should flush the first frame. subsequent frames of image will contain full valid data as the reset and read points will smoothly wrap around the imager. after the latency determined by the exposure programmed into the register, real image data is available at the output. pixel signal level pixel reset level 0 ? s0 ? s 2 r 2 r-1 2 r 2 c+m 2 c+1 2 c+2 2 c 2 r 0 ? s row reset(309:0) pixel signal sample column(107:0) column clamp row select(309:0) column power reset sample pixel reset sample exposure (ms) row blanking period row read period + rst_start_row ( sel_start_row ) ? = www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 12 region of interest it is possible to define the area of the pixel array the imager scans by writing to start_col, rst_start_row, sel_start_row, end_row and end_col registers. as seen in figure 12, the lower left-hand corner is used as the start address. data is written into the appropriate regis- ters as the number of rgb triplets from the left hand edge and the number of pixel rows from the bottom. for this cal- culation, all rows are taken into account. the end position of the scan is set by the appropriate regis- ters, writing it as the number of rgb triplets horizontally and the number of rows vertically. if none is defined, then default values are used. the registers are defined in the avr i/o space. pixels that are not read will not be reset other than through the user strobe frame reset (in still mode). it is not neces- sary however as the unread pixels will simply integrate up to saturation and no blooming effect will be visible. figure 11. region of interest ? calculation clocks in functional mode the chip requires three external clock pin connections. xin and xout connect the 16 mhz on- chip oscillator to an external crystal and lft connects the phase-locked-loop to an external low-pass filter. the combination produces two clock domains for use on- chip, 48 mhz and 9/12/16 mhz. the 48 mhz clock is the master clock, but only a small part of the logic is clocked at this frequency. the majority is clocked at a lower rate which is determined by the mode of operation. in usb mode, this clock is normally 12 mhz but may increase or decrease to 16 mhz or 9 mhz in order to syn- chronize with the usb serial stream. in parallel port mode, this clock runs at 16 mhz. (0,0) (324,310) (324,0) 0,0 is black pixel 324 pixel "triplets" 310 rows x block size x y block size (a,b) (c,d) c = end_col d = end_row a = start_col b = sel_start_row and rst_start_row a b www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 13 figure 12. external components with on-chip oscillator and pll reset the device has four hardware reset modes and one soft- ware reset mode. the first uses an on-chip power-on-reset cell which generates a reset pulse during device power-up. the second uses a dedicated input pin. the third applies to parallel port mode. the fourth applies to usb mode. the usb core detects a host request for a reset. the fifth is a software reset generated by setting a register control bit tg_cmd[4]. power control individual control over the main power-consuming blocks are provided by the ana_ctl register. the bias genera- tors, adc converters and analog amplifiers can be turned off to conserve power in standby. for low power operation, the master clock can also be reduced to a minimum of 1 mhz in parallel port mode. the clocks can also be suspended either in usb or parallel port mode using the usb host-suspend interface or the parallel port host-suspend operation. in either mode the avr shuts down the on-chip oscillator. an external signal from the usb or the parallel port will re-start the device. interrupt priority the device supports seven interrupts in total. table 3 gives information on the priority. notes: 1. for more details on these interrupts, refer to the par- allel port mode datasheet, literature number 1372. memory space the avr memory space is divided into three sections. the first allocation is for the avr i/o space registers. these are the 32 8-bit working registers (0x0000 to 0x001f) and the i/o registers (0x0020 to 0x005f). the second is for the 2k x 8 sram scratch pad memory (0x0800 to 0x0fff). the third is for the usb register map (0x1f00 to 0x1fff). xin xout lft 16 mhz r = 100 ? c1 = 33 pf c2 = 33 pf c3 = 10 nf table 3. usb interrupt priority interrupt description 1 usb (highest priority) 2 usb suspend and resume 3 (1) unused 4 (1) unused 5 (1) parallel port 6 (1) external interrupt 7 (1) unused www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 14 registers avr i/o space register map the 6-bit avr address bus allows for 64 possible i/o regis- ters with single-cycle accesses in conjunction with a read strobe (iore) and a write strobe (iowe). data is transferred on two separate 8-bit buses, shared for both i/o and data memory accesses; one for reads (dbusin[7:0]) and one for writes (dbusout[7:0]). see ? avr i/o registers ? on page 24 for detailed descriptions. table 4. avr i/o address map register i/o address memory address type default function imgbuf_preftch 0 0x00 0x20 read xxxxxxxxb image data fifo prefetch pp_cmd_in 1 0x01 0x21 read xx000000b parallel port command from host pp_data_in 2 0x02 0x22 read 00000000b parallel port data from host pp_stat_avr 3 0x03 0x23 bit 0: r/w bit 1-5: read xx000000b parallel port status (writing bit 0 resets the status bit) pp_cmd_out 4 0x04 0x24 write 00000000b parallel port command to host pp_data_out 5 0x05 0x25 write 00000000b parallel port data to host tg_cmd 9 0x09 0x29 write xx000000b timing generator command tg_stat_avr_rd 10 0x0a 0x2a read xxxxxx00b timing generator status tg_stat_avr_wr 11 0x0b 0x2b write xxxxxxx0b timing generator status shadow line_rd_mul 16 0x10 0x30 r/w xx000000b line multiplier for fifo loading end_col 17 0x11 0x31 r/w x1101011b end column address end_row_l 18 0x12 0x32 r/w 00110101b end row address (low byte) end_row_h 19 0x13 0x33 r/w xxxxxxx1b end row address (high byte) sel_start_row_l 20 0x14 0x34 r/w 00000000b start row select (low byte) sel_start_row_h 21 0x15 0x35 r/w xxxxxxx0b start row select (high byte) rst_start_row_l 22 0x16 0x36 r/w 00000000b start row reset (low byte) rst_start_row_h 23 0x17 0x37 r/w xxxxxxx0b start row reset (high byte) start_col 24 0x18 0x38 r/w x0000000b start column address image_capture_mo de 25 0x19 0x39 r/w 00000000b image capture mode led_int 26 0x3a r/w 10000000b led intensity ana_ctl 27 0x1b 0x3b r/w xxx00000b analog control register gainb 28 0x1c 0x3c r/w xx000000b gain right gaing 29 0x1d 0x3d r/w xx000000b gain center gain_mstr 30 0x1e 0x3e r/w xxxxxx00b gain global gainr 31 0x1f 0x3f r/w xx000000b gain left offb 32 0x20 0x40 r/w xxx00000b offset right offg 33 0x21 0x41 r/w xxx00000b offset center offr 34 0x22 0x42 r/w xxx00000b offset left www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 15 test_mode 35 0x23 0x43 r/w 00000000b test modes uart 36 0x24 0x44 bit 0: r/w bit bit 1: read only xxxxxxx0b uart data gpio 41 0x29 0x49 r/w 00000000b control port data gpio_dir 42 0x2a 0x4a r/w 11111111b control port direction fl_cmd_stat 45 0x2d 0x4d read 00000000b flash controller status fl_cmd_op 46 0x2e 0x4e r/w 00000000b flash controller opcode fl_cmd_adr1 47 0x2f 0x4f r/w 00000000b flash controller address register 1 fl_cmd_adr2 48 0x30 0x50 r/w 00000000b flash controller address register 2 fl_cmd_adr3 49 0x31 0x51 r/w 00000000b flash controller address register 3 fl_dbuf1 50 0x32 0x52 r/w 00000000b flash controller data buffer 1 fl_dbuf2 51 0x33 0x53 r/w 00000000b flash controller data buffer 2 fl_dlen_l 52 0x34 0x54 r/w 00000000b flash controller data buffer length (low byte) fl_dlen_h 53 0x35 0x55 r/w 00000000b flash controller data buffer length (high byte) 56 0x38 0x58 reserved for future avr release 57 0x39 0x59 reserved for future avr release 58 0x3a 0x5a reserved for future avr release rampz 59 0x3b 0x5b r/w 00000000b avr extended memory pointer register 60 0x3c 0x5c reserved for future avr release spl 61 0x3d 0x5d r/w 00000000b avr stack pointer low register sph 62 0x3e 0x5e r/w 00000000b avr stack pointer high register sreg 63 0x3f 0x5f avr status register table 4. avr i/o address map (continued) register i/o address memory address type default function table 5. scratch pad memory map memory address function 0x0800 - 0x0fff 2k x 8-bit memory www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 16 usb mode operation the usb mode is selectable via the status of the op_mode pin. by default this pin is set to logic level 0 using an internal pull down to configure the device in usb mode. it is therefore not shown in the pinout for the device in usb mode. the device appears to the host as a usb slave imaging device with three endpoints. endpoint 0 is a control endpoint with an 8-byte buffer endpoint 1 is a bulk in endpoint with a 64-byte buffer endpoint 2 is a interrupt endpoint with a 2-byte buffer table 6. usb register memory map register memory address default function frm_num_h 0x1ffd xxxxx000 frame number high register frm_num_l 0x1ffc xxxxx000 frame number low register glb_state 0x1ffb xxxxx000 global state register sprsr 0x1ffa xxxxx000 suspend/resume register sprsie 0x1ff9 xxxxxx00 suspend/resume interrupt enable register uisr 0x1ff7 00000000 usb interrupt status register uiar 0x1ff5 xxxxx000 usb interrupt acknowledge register uier 0x1ff3 xxxxx000 usb interrupt enable register faddr 0x1ff2 00000000 function address register endppgpg 0x1ff1 00000000 function endpoint ping-pong register ecr0 0x1fef 0xxx0000 endpoint0 control register ecr1 0x1fee 0xxx0000 endpoint1 control register ecr2 0x1fed 0xxx0000 endpoint2 control register csr0 0x1fdf x1110000 endpoint0 control and status register csr1 0x1fde x1110000 endpoint1 control and status register csr2 0x1fdd x1110000 endpoint2 control and status register fdr0 0x1fcf 00000000 fifo 0 data register fdr1 0x1fce 00000000 fifo 1 data register fdr2 0x1fcd 00000000 fifo 2 data register fbyte_cnt0_l 0x1fbf 00000000 byte count fifo 0 register [7:0] fbyte_cnt1_l 0x1fbe 00000000 byte count fifo 1 register [7:0] fbyte_cnt2_l 0x1fbd 00000000 byte count fifo 2 register [7:0] fbyte_cnt0_h 0x1faf 00000000 byte count fifo 0 register [10:8] fbyte_cnt1_h 0x1fae 00000000 byte count fifo 1 register [10:8] fbyte_cnt2_h 0x1fad 00000000 byte count fifo 2 register [10:8] www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 17 color filtering and color recovery the imager utilizes vertical stripes of pastel red, green and blue filtering laid over the pixels, which are rectangular with a height-to-width ratio of 2:1. black and white versions of the imager are available with- out the color filter layers but these still retain the rectangular pixels. figure 13. vertical stripe rgb color fiters to produce full color information for each pixel, the user must perform color recovery externally to the AT76C402, either in hardware or software. when low-resolution mode is used, full color recovery may not yield improved image quality due to the subsampling utilized in the imager. full color information is available vertically, and thus color recovery can be achieved simply by processing nine adja- cent pixels sequentially across the row in real time as they are read out of the imager. optimum color recovery is achieved by using a simple median filter transform (mft). this color recovery method is covered under us and international patents (us patents 4,663,665; 4,774,565 and 4,724,395) but a license to use this algorithm will be made available royalty free to be used only in conjunction with the AT76C402. as a working estimate, color recovery can be performed using less than 20,000 gates of logic. a full description of the color recovery method is available under nda and a diskette with example verilog and c- code is available on purchase of the device. figure 14. filter response characteristic diagram ? color filter transmission with cm500 ir cutoff rg b r g b rg b r g b rg b r g b rgb rgb rgb 6 m 12 m table 7. sensor optical performance description performance quantum efficiency of sensor pixel without color filters at 450 nm, 550 nm, 650 nm > 0.40 color filters rgb color stripes optical conversion including color filters > 40,000 e-/ux-s relative signal with same gain at 450 nm, 550 nm, 650 nm matched within 20% wavelength (nm) normalized response 0 0.5 1 400 500 600 700 www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 18 external memory interface eeprom mode at reset, a download state machine will read program code from an off-chip serial eeprom and store it into a program storage ram. the download state machine will load the entire ram space, even if the code size is smaller than the full range. the microcontroller will be held in reset by the state machine until the download is complete. the micro- controller will then begin execution from location 0000 in the ram. figure 15. eeprom read data timing diagram figure 16. eeprom write data timing diagram figure 17. eeprom control signal timing relationships 0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 instruction 15 14 13 3 2 1 6 5 4 3 2 1 0 7 cs sck si so high impedance data out byte address msb 0 012345678910112021222324252627282930 instruction 15 14 13 3 2 1 6 5 4 3 2 1 0 7 cs sck si so high impedance byte address 0 31 data in cs sck si so t css t wh v ih v il valid in v ih v il v ih v il t wl t csh t cs t su t h t v t ho t dis hi-z hi-z v oh v ol www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 19 flash memory mode in flash memory mode the spi interface is managed by a controller capable of reading and writing an external flash nonvolatile memory. the flash memory is configurable in two different configurations; first as a memory that holds program code for download at power-up and second as a memory that can receive and send image data. timing diagrams are provided below. note that there is a control signal (not shown in diagrams) that is not part of the eeprom interface. a ready/busy (spi_rdy) pin is driven low when the flash memory device is busy in an internally self-timed operation. this pin, which is normally in a high state (through an external pull-up resistor), is pulled low during programming operations, compare operations, and during page-to-buffer transfers. the busy status indicates that the flash memory array and one of the buffers cannot be accessed; read and write operations to the other buffer can still be performed. figure 18. main memory page program through buffers figure 19. buffer write figure 20. main memory page read cs si bfa7-0 pa6-0, bfa8 n pa6-0, bfa8 cmd rrrr, pa10-7 n + 1 last byte .... completes writing into selected buffer starts self-timed erase/program operation cs si bfa7-0 pa6-0, bfa8 n x...x,bfa8 cmd x n + 1 last byte .... completes writing into selected buffer 12345 cs sck si so high impedance data out msb 60 61 62 63 64 65 66 67 0 1 0 1 0 x x x x x d 7 d 6 d 5 command opcode t su t v www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 20 figure 21. buffer read figure 22. status register read 12345 cs sck si so high impedance data out msb 36 37 38 39 40 41 42 43 0 1 0 1 0 x x x x x d 7 d 6 d 5 command opcode t su t v 12345 cs sck si so high impedance msb 6 7 8 9 10 11 12 16 0 1 0 1 0 d 7 d 6 d 5 command opcode t su t v 17 1 1 1 d 1 d 0 d 7 lsb msb status register output www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 21 suggested lens information to be supplied. www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 22 packaging information to be supplied. figure 23. die and sensor location note: reference point (0, 0) is center of pad a. note: (0, 0) is center of pad in bottom right-hand corner. refer to figure 1 and figure 23. xy a to b -1960 3259 a to c -988 5119 table 8. AT76C402 pin and pad bond locations pad number pad name x (m) y (m) 1 vdddc -2473 7514 2 gnddc -3985 7514 7 vssac -5165 7514 8 vddac -5369 7514 18 ee_prgm -7494 6944 19 xout -7494 6846 20 xin -7494 6626 21 d0m -7494 6520 22 d0p -7494 6424 23 lft -7494 6310 30 vdddc -7493 5661 31 gnddc -7493 5571 sensor array a b c a : bottom right pad b : bottom left active pixel c : center of sensor active array 33 ee_si -7493 5389 35 ee_sclk -7493 5208 37 ee_cs -7493 5027 39 ee_so -7493 4845 49 vddac -7493 3938 50 vdddc -7493 3847 51 gndac -7493 3757 52 gnddc -7493 3666 58 vddac -7493 3122 59 gndac -7493 3031 70 vddac -7493 2024 71 gndac -7493 1933 79 ee_mode -7493 1208 82 gndvdc -7493 823 83 vdddc -7493 718 91 gndac -6782 0 92 vddac -6676 0 97 vdd_reg -6062 0 98 vdd5 -5837 0 99 avdd_reg -5634 0 100 avdd5 -5468 0 101 agnd -5243 0 102 agnd -5143 0 109 avdd -3754 0 110 agnd -3654 0 111 i_iar -2892 0 112 i_iag -2720 0 113 i_iab -2550 0 114 o_iar -2378 0 115 o_iag -2208 0 116 o_iab -2036 0 117 iref -1536 0 123 avdd -100 0 124 avdd 0 0 table 8. AT76C402 pin and pad bond locations pad number pad name x (m) y (m) www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 23 electrical specification notes: 1. i dd is with no load on all outputs. 2. v ih inputs are 5v-tolerant. 3. v oh is with i ol = 0.3 ma. 4. v ol low level output voltage is with i ol = 0.3 ma. 5. v ol leakage currents for outputs and bidirectional pads. table 9. absolute maximum ratings symbol parameter min typ max units v dd operating supply voltage -0.3 4.6 v v in dc input voltage -0.3 v dd + 0.3 v v out dc output voltage -0.3 v dd + 0.3 v temp operating free air temp -40 +85 c table 10. dc operating conditions symbol parameter min typ max units v dd operating supply voltage 3.0 3.3 3.6 v i dd overall supply current 70 ma v ih high level input voltage 0.7 x v dd v dd + 0.3 v v il low level input voltage 0 0.3 x v dd v v oh high level output voltage v dd - 0.1 v v ol low level output voltage v ss + 0.1 v leakage currents 100 na c i load digital input cap load 8 pf c o load digital output cap load 43 pf www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 24 avr i/o registers imgbuf_preftch register name: imgbuf_preftch description: one byte of image data from 8-bit fifo pp_cmd_in register name: pp_cmd_in description: parallel port command from 8-bit host pp_data_in register name: pp_data_in description: parallel port data from 8-bit host pp_stat_avr register name: pp_stat_avr description: parallel port status (8-bit) default: 00000000 pp_cmd_out register name: pp_cmd_out description: parallel port command to 8-bit host. note that any write to this register generates an interrupt to the host (signal b_pp_data[9]). values are firmware defined. bit value description 0000000 inactive 00000001 take image 00000010 abort 00000100 upload parameters 00001000 detect an image 00010000 download parameters 00100000 suspend bit value description bit 0 = 1 packet out (read/write-1-modify) bit 1 = 1 line in (read only) bit 2 = 1 host command pending (read only) bit 3 = 1 host data pending (read only) bit 4 = 1 asic command pending (read only) bit 5 = 1 asic data pending (read only) www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 25 pp_data_out register name: pp_data_out description: parallel port data to 8-bit host tg_cmd register name: tg_cmd description: timing generator command tg_stat_avr_rd register name: tg_stat_avr_rd description: timing generator status tg_stat_avr_wr register name: tg_stat_avr_wr description: timing generator status shadow line_rd_mul register name: line_rd_mul description: line multiplier for fifo loading default value: 0 value: number of additional line required on one side of the image data fifo before pingponging to the other side. this must satisfy the inequality: bit value definition 00000000 idle 00000001 read line (initiates line transfer to fifo) 00000010 start image readout 00000100 frame reset (only in still mode) 00001000 illumination led on (only in still mode) 00010000 abort readout (held while bit is high) 00100000 enter sleep mode bit value definition bit 0 1 line stored in image data fifo bit 1 0 parallel port mode 1 usb mode bit value definition bit 0 = 1 modify bit 1 of tg_stat_avr_rd line_rd_mul 1 + 64 3 end_col ( start_col 1 ) + () ? ? () ? > www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 26 end_col register name: end_col description: end column address default value: x1101011 end_row_l register name: end_row_l description: end row address (low byte) default value: 00110101 bit value description x0000000 pixel triplet corresponding to columns 1, 2, 3 x0000001 pixel triplet corresponding to columns 4, 5, 6 ... ... x1101010 pixel triplet corresponding to columns 319, 320, 321 x1101011 pixel triplet corresponding to columns 322, 323, 324 x1101100 out of range ... ... bit value description 00000000 row 1 00000001 row 2 ... ... 00110100 row 309 00110101 row 310 00110110 out of range ... ... www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 27 end_row_h register name: end_row_h description: end row address (high byte) default value: xxxxxxx1 sel_start_row_l register name: sel_start_row_l description: start of active row (low byte) default value: 00000000 sel_start_row_h register name: sel_start_row_h description: start of active row (high byte) default value: 00000000 bit value description xxxxxxx0 row 1 xxxxxxx0 row 2 ... ... xxxxxxx1 row 309 xxxxxxx1 row 310 xxxxxxx1 out of range ... ... bit value description 00000000 row 1 00000001 row 2 ... ... 00110100 row 309 00110101 row 310 00110110 out of range ... ... bit value description xxxxxxx0 row 1 xxxxxxx0 row 2 ... ... xxxxxxx1 row 309 xxxxxxx1 row 310 xxxxxxx1 out of range ... ... www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 28 rst_start_row_l register name: rst_start_row_l description: start of reset row (low byte) default value: 00000000 rst_start_row_h register name: rst_start_row_h description: start of reset row (high byte) default value: 00000000 start_col register name: start_col description: start column address default value: x0000000 bit value description 00000000 row 0 00000001 row 1 ... ... 00110100 row 308 00110101 row 309 00110110 out of range ... ... bit value description xxxxxxx0 row 0 xxxxxx0 row 1 ... ... xxxxxxx1 row 308 xxxxxxx1 row 309 xxxxxxx1 out of range ... ... bit value description x0000000 pixel triplet corresponding to columns 1, 2, 3 x0000001 pixel triplet corresponding to columns 4, 5, 6 ... ... x1101010 pixel triplet corresponding to columns 319, 320, 321 x1101011 pixel triplet corresponding to columns 322, 323, 324 x1101100 out of range ... ... www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 29 image_capture_mode register name: image_capture_mode description: image capture mode default value: 00000000 led_int register name: led_int description: led intensity default value: 10000000 bit value description bit 0 0 truncated data 1 lookup table bit 1 0 lookup table a 1 lookup table b bit 2 0 still mode 1 continuous mode bit 3 0 illumination led active 1 illumination led powered down bit 4 0 buf_12m clock to external clock pin 1 buf_12m/2 clock to external clock pin bit 5 0 parallel port not in program counter mode 1 program counter output bit 6 0 illumination led pulsed 1 illumination led continuous bit 7 0 indicator led on 1 indicator led off bit value description 00000000 zero 00000001 1/255th full brightness 00000010 2/255th full brightness ... ... 11111110 254/255th full brightness 11111111 full brightness www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 30 ana_ctl register name: ana_ctl description: analog control register gainb register name: gainb description: gain left default value: 00000000 bit value description bit 0 = 1 power down a-to-d bit 1 = 1 power down image array bit 2 = 1 power down gain and offset bit 3 = 1 test mode bit 4 = 1 gamma mode bit 7:5 don ? t care bit value definition xx000000 1.00x gain xx000001 1.03x gain xx000010 1.06x gain xx000011 1.09x gain xx000100 1.12x gain ... ... xx111110 2.86x gain xx111111 2.89x gain www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 31 gaing register name: gaing description: gain center default value: 00000000 gain_mstr register name: gain_mstr description: gain global default value: 00000000 gainr register name: gainr description: gain right default value: 00000000 bit value definition xx000000 1.00x gain xx000001 1.03x gain xx000010 1.06x gain xx000011 1.09x gain xx000100 1.12x gain ... ... xx111110b 2.86x gain xx111111b 2.89x gain bit value definition xxxxxx00 1x gain xxxxxx01 2x gain xxxxxx10 4x gain xxxxxx11 8x gain bit value definition xx000000 1.00x gain xx000001 1.03x gain xx000010 1.06x gain xx000011 1.09x gain xx000100 1.12x gain ... ... xx111110 2.86x gain xx111111 2.89x gain www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 32 offb register name: offb description: offset left default value: 00000000 offg register name: offg description: offset center default value: 00000000 offr register name: offr description: offset right default value: 00000000 bit value definition xxx00000 -2.4 a xxx00001 -2.4 a ... ... xxx01100 0 a ... ... xxx11110 +3.6 a xxx11111 +3.8 a bit value definition xxx00000 -2.4 a xxx00001 -2.4 a ... ... xxx01100 0 a ... ... xxx11110 +3.6 a xxx11111 +3.8 a bit value definition xxx00000 -2.4 a xxx00001 -2.4 a ... ... xxx01100 0 a ... ... xxx11110 +3.6 a xxx11111 +3.8 a www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 33 test_mode register name: test_mode description: engineering and manufacturing test modes default value: 00000000 uart register name: uart description: uart port data. the receive input is synchronized to the internal 12/16 mhz clock rising edge. gpio register name: gpio description: control port data (bidirectional with status as input or output set by gpio_dir register). gpio inputs are synchronized to the internal 12/16 mhz clock rising edge. mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 normal operation xxxxx000 pll test mode xxxxx001 spi test mode xxxxx010 lut rom xxxxx011 avr & usb scan xxxxx100 not used 0 0 x x x 1 0 1 isa column counter only 0 1 x x x 1 0 1 isa row select counter only 1 0 x x x 1 0 1 isa row reset counter only 1 1 x x x 1 0 1 isa control signals 0xxxx110 isa control signals with inverted data 1xxxx110 bit value definition bit 0 pin tx (output) bit 1 pin rx (input) bit value description bit 0 pin cp<0> bit 1 pin cp<1> bit 2 pin cp<2> bit 3 pin cp<3> bit 4 pin cp<4> bit 5 pin cp<5> bit 6 pin cp<6> bit 7 pin cp<7> www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 34 gpio_dir register name: gpio_dir description: control port direction (specifies whether corresponding bit in gpio is read or write fl_cmd_stat register name: fl_cmd_stat description: flash controller status. see ? external memory interface ? on page 18 for timing diagrams. bit value description bit 0 pin cp<0> 0output 1 input bit 1 pin cp<1> 0output 1 input bit 2 pin cp<2> 0output 1 input bit 3 pin cp<3> 0output 1 input bit 4 pin cp<4> 0output 1 input bit 5 pin cp<5> 0output 1 input bit 6 pin cp<6> 0output 1 input bit 7 pin cp<7> 0output 1 input bit value description bit 0 0 ready 1busy bit 1 1 done bit 3 1 data buffer 1 busy bit 4 1 data buffer 2 busy bit 6 0write 1read bit 7 1 start www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 35 fl_cmd_op register name: fl_cmd_op description: flash controller opcode. see ? external memory interface ? on page 18 for timing diagrams. fl_cmd_adr1 register name: fl_cmd_adr1 description: flash controller address register 1 fl_cmd_adr1 register name: fl_cmd_adr2 description: flash controller address register 2 fl_cmd_adr1 register name: fl_cmd_adr3 description: flash controller address register 3 fl_dbuf1 register name: fl_dbuf1 opcodes description 0x52 main memory page read 0x53 main memory page to buffer 1 transfer 0x54 buffer 1 read 0x55 main memory page to buffer 2 transfer 0x56 buffer 2 read 0x57 status register 0x58 auto page rewrite through buffer 1 0x59 auto page rewrite through buffer 2 0x60 main memory page to buffer 1 compare 0x61 main memory page to buffer 2 compare 0x82 main memory page program through buffer 1 0x83 buffer 1 to main memory page program with built-in erase 0x84 buffer 1 write 0x85 main memory page program through buffer 2 0x86 buffer 2 to main memory page program with built-in erase 0x87 buffer 2 write 0x88 buffer 1 to main memory page program without built-in erase 0x89 buffer 2 to main memory page program without built-in erase www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 36 description: flash controller data buffer 1 fl_dbuf2 register name: fl_dbuf2 description: flash controller data buffer 2 fl_dlen_l register name: fl_dlen_l description: flash controller data buffer length (low byte) fl_dlen_h register name: fl_dlen_h description: flash controller data buffer length (high byte) rampz register name: rampz description: avr extended memory pointer register default: 00000000b spl register name: spl description: avr pointer low register default: 00000000b sph register name: sph description: avr pointer high register default: 00000000b bit value definition bit 0 0 low memory page (0x0000 - 0x7fff) 1 high memory page (0x8000 - 0xffff) www.datasheet.co.kr datasheet pdf - http://www..net/
AT76C402 ? usb 37 sreg register name: sreg description: avr status register bit value description bit 0 carry flag 1 carry in arithmetic or logic operation bit 1 zero flag 1 zero result after arithmetic or logic operation bit 2 negative flag 1 negative result after arithmetic or logic operation bit 3 two ? s complement overflow flag 1 two ? s complement arithmetic bit 4 sign bit 1 exclusive or between negative flag & two ? s complement overflow flag bit 5 half-carry flag 1 half carry in arithmetic operation bit 6 bit copy storage 1 storage location for bit copy operation bit 7 global interrupt enable 0 interrupts disabled 1 interrupts enabled www.datasheet.co.kr datasheet pdf - http://www..net/
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